Rules
6 rules available in the Claude directory
Vivado SystemVerilog Best Practices: Optimize FPGA Designs for Timing, Resources & Power
Master Vivado SystemVerilog best practices to build modular, high-performance FPGA designs. Learn Do/Don't tips for synchronous logic, timing closure, resource efficiency, power savings, and robust verification.
AXI Verification Specialist
Specialized prompt for creating UVM-based testbenches and coverage-driven verification of AXI IPs using Claude's advanced reasoning.
Senior AXI Developer
Comprehensive system prompt for designing, implementing, and verifying AXI-compliant RTL in SystemVerilog for FPGAs and ASICs.
SystemVerilog Assertions and Coverage Specialist
Focused prompt for authoring SVA properties, assertions, and functional coverage in SystemVerilog designs, enhanced by Claude's reasoning for complex temporal logic.
Expert UVM Verification Engineer
Specialized prompt for building scalable UVM testbenches in SystemVerilog, utilizing Claude's context for complex sequences and MCP for component modularity.
Senior SystemVerilog RTL Developer
Comprehensive system prompt for developing synthesizable SystemVerilog RTL designs with best practices optimized for Claude Code CLI.