Rules
7 rules available in the Claude directory
Vivado AXI Data Transfer Optimization: Best Practices for High-Performance FPGA Design
Boost FPGA efficiency with proven AXI protocol strategies in Vivado. Discover essential tips for DMA integration, backpressure management, buffer alignment, and verification to achieve optimal throughput and low latency.
Vivado SystemVerilog Best Practices: Optimize FPGA Designs for Timing, Resources & Power
Master Vivado SystemVerilog best practices to build modular, high-performance FPGA designs. Learn Do/Don't tips for synchronous logic, timing closure, resource efficiency, power savings, and robust verification.
Senior AXI Developer
Comprehensive system prompt for designing, implementing, and verifying AXI-compliant RTL in SystemVerilog for FPGAs and ASICs.
Senior SystemVerilog RTL Developer
Comprehensive system prompt for developing synthesizable SystemVerilog RTL designs with best practices optimized for Claude Code CLI.
FPGA Timing and Debug Expert
Specialized prompt for debugging, timing analysis, and optimization in FPGA flows to achieve reliable high-speed designs.
High-Level Synthesis FPGA Specialist
Prompt for HLS-based FPGA development accelerating C/C++ to RTL for algorithms like ML inference or signal processing.
Senior FPGA Engineer
Comprehensive system prompt for expert FPGA development covering HDL, synthesis, verification, and optimization.