Conference Paper
Machine Learning

The McPAT Framework for Multicore and Manycore Architectures

Sheng Li(Hewlett-Packard (United States)), Jung Ho Ahn(Seoul National University), Richard Strong(University of California San Diego), Jay Brockman(University of Notre Dame), Dean M. Tullsen(University of California San Diego), Norman P. Jouppi(Hewlett-Packard (United States))
April 1, 2013ACM Transactions on Architecture and Code Optimization231 citations
PDFDOI

231

Citations

25

Influential Citations

ACM Transactions on Architecture and Code Optimization

Venue

2013

Year

Abstract

This article introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At microarchitectural level, McPAT includes models for the fundamental components of a complete chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, and integrated system components such as memory controllers and Ethernet controllers. At circuit level, McPAT supports detailed modeling of critical-path timing, area, and power. At technology level, McPAT models timing, area, and power for the device types forecast in the ITRS roadmap. McPAT has a flexible XML interface to facilitate its use with many performance simulators. Combined with a performance simulator, McPAT enables architects to accurately quantify the cost of new ideas and assess trade-offs of different architectures using new metrics such as Energy-Delay-Area2 Product (EDA2P) and Energy-Delay-Area Product (EDAP). This article explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting trade-offs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies from cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks for manycore designs at the 22nm technology shows that 8-core clustering gives the best energy-delay product, whereas when die area is taken into account, 4-core clustering gives the best EDA2P and EDAP.

Analysis

Why This Paper Matters

This paper introduces McPAT, a comprehensive framework that addresses a critical gap in computer architecture research: the need for integrated power, area, and timing modeling across multiple abstraction levels. As multicore and manycore processors become increasingly complex, architects require tools that can accurately estimate the cost of new ideas and assess trade-offs early in the design cycle. McPAT fills this need by providing a unified platform that spans from microarchitectural components (cores, networks-on-chip, caches) down to circuit-level and technology-level models based on the ITRS roadmap. Its flexible XML interface allows seamless integration with existing performance simulators, making it a practical tool for both academia and industry.

The paper's focus on clustering in manycore processors is particularly timely, as it highlights the trade-offs between area and performance that arise from grouping cores. By introducing new metrics like EDA2P and EDAP, McPAT enables a more holistic evaluation that goes beyond traditional energy-delay products, accounting for the increasing importance of die area in modern chip design.

Technical Contributions

  • Integrated multi-level modeling: Combines microarchitectural, circuit-level, and technology-level models in a single framework, covering in-order and out-of-order cores, networks-on-chip, shared caches, memory controllers, and Ethernet controllers.
  • Technology scaling support: Models timing, area, and power for device types forecast in the ITRS roadmap, supporting configurations from 90nm to 22nm and beyond.
  • Flexible XML interface: Enables easy integration with various performance simulators, allowing architects to plug McPAT into existing workflows.
  • New evaluation metrics: Introduces Energy-Delay-Area2 Product (EDA2P) and Energy-Delay-Area Product (EDAP) to capture area costs alongside energy and delay.
  • Clustering analysis: Demonstrates the framework's utility by exploring clustering trade-offs in manycore processors at 22nm, showing that optimal cluster size depends on the metric used.

Results

Using McPAT combined with performance simulation of PARSEC benchmarks for manycore designs at 22nm technology, the paper reports:

  • 8-core clustering gives the best energy-delay product.
  • 4-core clustering gives the best EDA2P and EDAP when die area is taken into account.
  • The analysis highlights that clustering introduces area overhead from interconnects but enables cache sharing synergies, leading to trade-offs that vary by application.

Significance

McPAT has become a widely used tool in computer architecture research (231 citations), enabling systematic design space exploration that was previously difficult or ad hoc. By providing a standardized framework for power, area, and timing modeling, it allows researchers to fairly compare different architectural innovations and make informed trade-offs. The introduction of area-aware metrics like EDA2P and EDAP is particularly important as chip costs become increasingly dominated by die area. The framework's flexibility and open XML interface have facilitated its adoption across many research groups, making it a foundational tool for multicore and manycore architecture studies.

power-modelingarea-modelingtiming-modelingmulticoremanycoredesign-space-explorationxml-interfaceitrs-roadmap
Benchmarks

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