Conference Paper
Machine Learning

T-CREST: Time-predictable multi-core architecture for embedded systems

Martin Schoeberl(Technical University of Denmark), Sahar Abbaspour(Technical University of Denmark), Benny Åkesson(Czech Technical University in Prague), Neil Audsley(University of York), Raffaele Capasso(INTECS (Italy)), Jamie Garside(University of York), Kees Goossens(Eindhoven University of Technology), Sven Goossens(Eindhoven University of Technology), Scott D. Hansen, Reinhold Heckmann(AbsInt (Germany)), Stefan Hepp(TU Wien), Benedikt Huber(TU Wien), Alexander Jordan(Technical University of Denmark), Evangelia Kasapaki(Technical University of Denmark), Jens Knoop(TU Wien), Yonghui Li(Eindhoven University of Technology), Daniel Prokesch(TU Wien), Wolfgang Puffitsch(Technical University of Denmark), Peter Puschner(TU Wien), André Rocha(GMV Innovating Solutions (Portugal)), Cláudio Silva(GMV Innovating Solutions (Portugal)), Jens Sparsø(Technical University of Denmark), Alessandro Tocchi(INTECS (Italy))
April 11, 2015Journal of Systems Architecture218 citations
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218

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8

Influential Citations

Journal of Systems Architecture

Venue

2015

Year

Abstract

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding. The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7. The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.

Analysis

Why This Paper Matters

Real-time embedded systems, such as those in avionics and railway control, require guarantees on worst-case execution time (WCET) to ensure safety. Standard multi-core processors are optimized for average-case performance, making static WCET analysis extremely difficult due to unpredictable resource sharing. T-CREST addresses this critical gap by designing a complete multi-core architecture from the ground up for time-predictability, rather than average-case throughput. This paradigm shift is essential for the adoption of multi-core processors in safety-critical systems, where certification standards demand analyzable timing behavior.

The paper is significant because it demonstrates that time-predictable design does not necessarily sacrifice performance in the WCET sense. By optimizing for WCET, T-CREST achieves substantial speedups (up to 5.7× with 15 cores) for computation-intensive tasks, showing that predictability and performance can coexist. This work is a collaborative effort of eight academic and industrial partners, indicating broad relevance and validation.

Technical Contributions

  • Time-predictable processor core: Designed to have a constant execution time per instruction, simplifying WCET analysis.
  • Network-on-chip (NoC): Provides predictable communication latency between cores, avoiding bus contention.
  • Time-predictable memory arbiter and controller: Ensures that memory accesses do not cause unpredictable delays.
  • WCET-aware compiler: Optimizes code for worst-case paths rather than average-case paths.
  • Static WCET analysis tool: Integrated with the architecture to provide tight WCET bounds.
  • Industrial validation: Two use cases (avionic and railway) demonstrate real-world applicability.

Results

  • Avionic application: Tasks on different cores show no WCET interference, confirming isolation.
  • Railway signal processing: WCET improved by factor 1.8 with 3 cores and 5.7 with 15 cores compared to single-core execution.
  • The platform is evaluated with real industrial workloads, not just synthetic benchmarks.

Significance

T-CREST provides a blueprint for designing time-predictable multi-core systems that can be certified for safety-critical applications. Its approach of co-designing hardware and tools (compiler, WCET analysis) is a model for future real-time architectures. The demonstrated WCET improvements show that multi-core parallelism can be harnessed without sacrificing predictability, which is crucial for domains like autonomous driving, aerospace, and industrial automation. The open-source nature of the project (implied by collaborative research) also enables further research and adoption.

real-time-systemsmulti-core-architecturewcet-analysistime-predictabilityembedded-systemsnetwork-on-chipcompiler-optimization

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